1. Field of the Invention
The present invention relates to a semiconductor device having a dual-gate structure.
2. Description of Related Art
As in recent years, electronic devices have become lighter in weight and smaller in size, as well as higher in performance, it is called on to develop smaller-size and higher-performance semiconductors for use in these electronic devices.
For a dual-gate structured semiconductor device 100 having a gate electrode composed of a N-type conductive layer and a P-type conductive layer as shown in FIG. 6A to address such a need for miniaturization, it is necessary to narrow the gate width of a gate electrode 106 straddling (extending across) a N-type transistor formation region 102 and a P-type transistor formation region 104 to reduce an layout area (defined by the areas of the N-type transistor formation region 102 and of the P-type transistor formation region 104).
When the gate width of the gate electrode 106 is narrowed, however, a metal silicide layer deposited on the gate electrode 106, may peel off or agglutinate locally (in the proximity of the boundary L between the N-type transistor formation region 102 and the P-type transistor formation region 104), causing a defective portion to be formed therein. For this reason, a problem has risen that abnormally-high electric resistance occurs in the gate electrode 106.
To resolve this problem, a semiconductor device 110 having a planar structure (the disclosure of which is incorporated by reference herein) as shown in FIG. 6B has been proposed.
A gate electrode 116 of the semiconductor device 110 (the disclosure of which is incorporated by reference herein) is structured so that it has a gate width widened in the proximity of the boundary L between an N-type transistor formation region 112 and a P-type transistor formation region 114. In this way, the gate width of the gate electrode 116 may be widen without widening the overall gate width of the gate electrode 116 to prevent the metal silicide layer deposited on the gate electrode 116 from peeling off or agglutinating, successfully suppressing the formation of a defective portion therein.
Since the layout area, however, is substantially determined by the gate width of the gate electrode 116 in the proximity of the boundary, widening the gate width of the gate electrode 116 in the proximity of the boundary L involves the enlargement of the layout area, inevitably leading to the larger-size semiconductor device 110.